Business Wire

Silvaco and OPENEDGES Announce Availability of Integrated DDR Controller and PHY IP Solutions

SANTA CLARA, Calif. & SEOUL, South Korea--(BUSINESS WIRE)--Silvaco, Inc., a leading supplier of EDA software and design IP, today announced a collaboration with OPENEDGES Technology, Inc., a leading ...
Electronic Design

A Summary Of The DDR Memory Controller Standard—Wait, There Isn’t One!

The number of systems-on-a-chip (SoCs) that require an interface to off-chip memory is increasing. As a result, more and more designers are turning to double-data-rate (DDR) SDRAM interfaces such as ...
EDN

ESC – New Synopsys Universal DDR Controllers Improve Performance and Reduce Cost of Embedded DRAM Interfaces

Mountain View, Calif. – Synopsys, Inc. today announced the availability of the high-performance DesignWare Universal DDR Protocol and Memory Controllers, both supporting the DDR2, DDR3, Mobile DDR and ...
EDN

Dual PWM controller powers DDR, graphics, chip sets

Milpitas, Calif. – Intersil's ISL6227 is a dual PWM controller IC designed to power DDR memory, graphics, chip sets and other systems in notebook PCs. Its wide input voltage range capability allows ...
Electronic Design

Mobileye sees Denali DDR controller IP in automotive systems

Mobileye N.V. (www.mobileye.com) has licensed Databahn DDR memory controller intellectual property from Denali Software (www.denali.com) for use in Mobileye’s EyeQ2 Vision system-on-chip. Nov. 27, ...
TechRepublic

Implementation of DDR SDRAM Controller Using Verilog HDL

Now-a-days, DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) has become the most popular class of memory used in computers due to its high speed, burst access and pipeline feature ...
Design News

Optimizing LPDDR and DDR Memory for Cutting-Edge Apps

The role of memory to handle an avalanche of data expected in future leading-edge applications such as automotive and artificial intelligence has led to product innovations from several companies, the ...
Semiconductor Engineering

DDR Memory Test Challenges From DDR3 to DDR5

Cloud, networking, enterprise, high-performance computing, big data, and artificial intelligence are propelling the development of double data rate (DDR) memory chip technology. Demand for lower power ...

Explaining AMD gear modes and why they’re important for intensive workloads

How AMD Gear 1 and Gear 2 balance memory speed, latency, and bandwidth for different workloads.
Design-Reuse

OPENEDGES Advances Commercialization of LPDDR6/5X Memory Subsystem IP, Targeting Next-Generation AI and HPC Markets

Seoul, South Korea -- OPENEDGES Technology, a leading provider of memory subsystem IP solutions, today announced that it has secured its first license agreement for memory subsystem IP supporting both ...